1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module, and relates in particular to a technique for preventing a defect due to the mismatching of thermal expansion coefficients when a semiconductor device is mounted on a substrate.
2. Description of the Related Art
To produce a hybrid integrated circuit for installation in an electronic apparatus, a conductive pattern is formed on a printed circuit board, a ceramic substrate or a metal substrate, and an active element, such as an LSI or a discrete TR, and a passive element, such as a chip capacitor, a chip resistor or a coil, are mounted thereon. The conductive pattern and these elements are electrically connected to provide a circuit capable of performing a predetermined function.
FIG. 24 is a diagram of such a circuit, an audio circuit, the elements of which are mounted as shown in FIG. 25.
In FIG. 25, straight, peripheral lines describe a rectangular substrate 1 having a surface that is, at the least, insulated. Adhered thereto is a conductive pattern 2, composed of Cu. The conductive pattern 2 is composed of an external connecting electrode 2A, a wire line 2B, a die pad 2C, a bonding pad 2D, and an electrode 4, fixed to the passive element 3.
A bare chip, consisting of a TR, a diode, a composite element or an LSI, is soldered to the die pad 2C, and the electrode on the chip and the bonding pad 2D are electrically connected by fine metal lines 5A, 5B and 5C, each of which is generally divided into a low signal portion and a high signal portion. An Au or Al line 5A of about 40 xcexcm xcfx86 is employed for the low signal portion, and an Au or Al line of about 100 to 300 xcexcm xcfx86 is employed for the high signal portion. Especially, since the high signal portion has a large diameter, while taking manufacturing costs into account, an Al line 5B of 150 xcexcm xcfx86 and an Al line 5C of 300 xcexcm xcfx86 are employed.
A power TR 6 though which a large current flows is securely fixed to a heat sink 7 on a die pad 2C in order to prevent a rise in the temperature of the chip.
The line 2B is extended to various locations in order to form the circuit for the external drawing electrode 2A, the die pad 2C, the bonding pad 2D and the electrode 4. Further, when lines intersect each other because of their disposition on the chip and when they must be extended, jumper lines 8A and 8B are employed.
An example semiconductor device to be mounted in the substrate 1 is a semiconductor device packaged using an insulating resin. As such a packaged semiconductor device there is a lead frame type semiconductor device, wherein a semiconductor chip is mounted in a lead frame and the resultant structure is packaged using an insulating resin; a support substrate type semiconductor device, wherein a semiconductor chip is mounted on a ceramic support substrate, a printed circuit board or a flexible sheet, and the resultant structure is packaged using an insulating resin; or a plated type semiconductor device, wherein a semiconductor chip is mounted on a plated electrode and the resultant structure is packaged. It should be noted that the plated type semiconductor device is described in detail in JP-A-3-94431.
FIG. 26A is a schematic diagram showing the plated type semiconductor device. Conductive paths 10A to 10D are formed of a plated film, a semiconductor chip 11 is securely bonded to the die pad 10A, and the bonding pad on the semiconductor chip 11 and the plated bonding pad 10B are electrically connected by a fine metal line 12. A passive element 13 is bonded between the electrodes 10C and 10D via a brazing material. And since the plated film is embedded in the insulating resin without using a support substrate, a thin semiconductor device can be provided.
As is described above, a semiconductor device packaged using various methods is mounted on the substrate 1. However, when a lead frame type semiconductor device is packaged, since lead projects outward from the package, the area of the substrate occupied by the device is expanded, and the size of the substrate must accordingly be increased. In addition, the lead frame could be cut or a burr could be left on the lead. Furthermore, for the support substrate type semiconductor device, since a support substrate is employed, the semiconductor device will be thicker, and accordingly, the weight of the device will be increased. Further, although a thin and compact plated type semiconductor device can be made because no support substrate is employed and because no lead projects outward from the package, the following problem has arisen.
For the explanation of the problem, in FIG. 26B an enlarged diagram is shown of a portion enclosed by a broken-line circle in FIG. 26A. Included in this portion is a conductive path 10B, which is formed by plating and is represented as a set of trigonal pyramids; solder 17; a substrate 15; and a conductive pattern 16 adhered to the substrate 15.
The plated film is generally deposited by electrolytic plating, and has a crystal structure that assumes a tapered pillar shape. This structure is represented by using the trigonal pyramids. Since when formed the plated film is thin and has a polycrystalline structure, it is mechanically weak, and cracks tend to occur due to differences in the thermal expansion coefficient of the insulating resin. In addition, the grain boundary easily diffuses an externally supplied material. Thus as one problem, the flux used for soldering or an external ambient gas, such as moisture, may enter via the connection for the fine metal line 12, and at the grain boundary, cause deterioration of the connection strength. Further, as another problem, when an electrode 10B is formed using Cu plating, the solder layer underneath is diffused and eats into the plated film, thereby deteriorating the strength of the connection with the fine metal line.
In addition, when an elongated plated film is formed as a wire line, line disconnection may occur due to mismatching with the thermal expansion coefficient of the insulating resin. Similarly, when the plating type semiconductor device is mounted in the substrate, cracks also occur in wire lines due to mismatching with the thermal expansion coefficient of the substrate, and causes line disconnections or increases in line resistance. Especially when a long wire line is formed using the plated electrode 10B, stress is generated in proportion to the length. Therefore, differences in the thermal expansion coefficient of the insulating resin 14 or the substrate 15 aggravates defects in the plated film and degrades reliability even more.
To resolve these shortcomings, according to a first aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of a conductive material whose crystal growth is large in the X and Y directions;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin which is coated on the semiconductor chip and fills separation grooves between the conductive paths, thereby integrally supporting the conductive paths while the back surfaces of the conductive paths are exposed.
As is shown in FIG. 1A, a film that experiences more growth along the Z axis than along the X-Y axis is called a Z film, and a film that experiences more growth along the X-Y axis than along the Z axis is called an X-Y film. The Z film may be a plated film grown using an electrolytic process or an electroless process, and the X-Y film is a film, such as rolled copper foil, formed by rolling.
As is shown in the cross section of the X-Y film in FIG. 1C, since the individual crystals are laminated, spreading along the X-Y axis, the area size of the grain boundary is smaller than the Z film in FIG. 1A. Therefore, the phenomenon of diffusion or transmission through the grain boundary is considerably restricted. The Z film in FIG. 1B is so structured that it is very weak and is susceptible to the stress produced when the structure is bent and extended horizontally by an external force. Further, as is shown in FIG. 1C, the X-Y film is more resistant to warping and tearing than is the Z film. Therefore, the occurrence of cracks in a conductive path because of differences in the thermal expansion coefficients of the insulating resin that seals the conductive path can be prevented. Further, since the crystal size is large, the overall resistance of the conductive paths can also be reduced. Especially when the conductive paths are to be embedded in a package having a thickness of 0.5 mm or less, since the plane size is greater than the thickness, stress is exerted in the X-Y direction due to differences in the thermal expansion coefficients of the conductive path and the insulating resin. However, since each crystal experiences extensive growth in the X-Y direction, greater structural resistance to stress can be obtained.
When an electrode composed of rolled copper foil that is embedded in insulating resin is compared with a copper plated electrode that is likewise embedded, the rolled copper foil electrode is superior in strength and can better resist stress, and at the contact portion is also less contaminated due to diffusion.
According to a second aspect, the back surface of the insulating resin and the side walls of the conductive paths are substantially on the same etching plane.
As is obvious when considering a manufacturing method that will be described later, since these faces are half-etched and the insulating resin is later embedded therein, the insulating resin assumes the shape of the curved structure obtained by half-etching. This structure not only provides anchoring effects, but also reduces contact resistance on the back surface. Therefore, the movement and the self-alignment of the semiconductor device are facilitated.
According to a third aspect of the invention, the back surfaces of the conductive paths are formed so that they are recessed more than are the back surfaces of the separation grooves.
Since the conductive paths are recessed, a thick soldered portion can be formed on the conductive paths, and since the convex portion of the insulating resin is formed, the adjacent soldered portions do not contact each other.
According to a fourth aspect of the invention, an oxide of the conductive material is deposited on the upper surfaces of the conductive paths that contact the insulating resin.
Since a copper oxide is deposited on the upper surface of each conductive path, especially the surface of a metal that contains copper as the main material, the conductive paths can be more closely attached to the insulating resin.
According to a fifth aspect of the invention, the insulating film is substantially thinner than 1 mm, and the conductive paths are thick enough that they can be processed using the rolling method.
According to a sixth aspect, a semiconductor device comprises:
a plurality of conductive paths formed of crystal that grows better along the X and Y axes than along the Z axis;
a conductive film deposited on the upper faces of the conductive paths that is formed mainly of crystal and that grows better along the Z axis than along the X and Y axes;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed.
In principle, when the conductive patterns that serve as electrodes and wire lines are formed of the X-Y film, and the Z film is grown only on the portion whereat an electrical connection is required, a superior characteristic can be obtained compared with when all the conductive patterns are formed of the Z film. Thus, a semiconductor device is resistant to line disconnection or contamination at a joint.
According to a seventh aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of crystal that grows better along the X and Y axes than along the Z axis;
a conductive film deposited on the upper faces of the conductive paths and formed mainly of crystal that grows better along the Z axis than along the X and Y axes;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed.
wherein the back surface of the insulating resin and the side walls of the conductive paths are substantially on the same etching plane.
According to an eighth aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of crystal that grows better along the X and Y axes than along the Z axis;
a conductive film, deposited on the upper faces of the conductive paths, for which, because of plating, crystal growth is greater mainly along the Z axis
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed,
wherein the etched side walls of the conductive paths are curved, and the curve formed in the etched side walls continues across at least a part of the back surface of the insulating resin.
According to a ninth aspect of the invention, non-anisotropic etching is used to form in the etched side walls the curve that is continued.
According to a tenth aspect of the invention, the back surfaces of the conductive paths are recessed more than is the back surface of the insulating resin.
According to an eleventh aspect of the invention, an oxide is deposited on the upper surfaces of the conductive paths contacting the insulating resin.
According to a twelfth aspect of the invention, a conductive film is deposited on the back surfaces of the conductive paths.
When the back surface of a conductive path is coated with metal film or soft solder, oxidization of the conductive path can be prevented. Therefore, even when the circuit pattern on the substrate is connected to a conductive path by brazing material, the chance of a connection failure can be considerably reduced because no oxide film is deposited on the conductive path.
According to a thirteenth aspect of the invention, the conductive film can be provided by forming eaves on the upper surfaces of the conductive paths.
Since the conductive paths and the conductive film, or the conductive paths themselves can implement the processing for the shaping of the eaves, anchoring effects can be obtained, and the slipping or the peeling of the conductive path can be prevented.
According to a fourteenth aspect of the invention, the conductive paths that are exposed and free of the insulating resin are covered by an insulating film, except for portions at electrical connections.
When conductive paths having various shapes are employed, the wetting of brazing material, such as solder, may occur across the entire area. Therefore, not only the volume but also the thickness of soft solder differs, depending on the size, the surface tension and the weight of the solder itself. And thus, when a film that is resistant to the wetting to which solder is susceptible is deposited on exposed conductive paths, the area whereat wetting of the solder occurs is reduced, and solder having a desired thickness can be formed on the back surfaces of the conductive paths.
According to a fifteenth aspect of the invention, wire lines are provided as the conductive paths, and the conductive paths that are exposed and free of the insulating resin are covered by an insulating film, except for portions at electrical connections.
The semiconductor device is so designed that the back surfaces of the conductive paths are exposed and free of the insulating resin. Thus, the back surfaces of lines shown in FIGS. 6, 7 and 11 are also exposed and extended long distances. Therefore, when the semiconductor device is mounted in a substrate, the lines and the conductive pattern in the substrate short-circuit. This short-circuiting is prevented, however, by depositing the insulating film that covers the back surfaces of the lines.
According to a sixteenth aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths composed of a conductive material whose crystal growth is greater along the X and Y axes than along the Z axis;
a conductive film deposited on the upper faces of the conductive paths and formed mainly by the growth of crystal along the Z axis;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed,
wherein the semiconductor device is mounted in the substrate via an exposed portion.
According to a seventeenth aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of a conductive material whose crystal growth is greater along the X and Y axes than along the Z axis;
a conductive film deposited on the upper faces of the conductive paths and formed mainly by the growth of crystal along the Z axis;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed,
wherein the back surface of the insulating resin and the side walls of the conductive paths substantially for a continuous curve, and
wherein the semiconductor device is mounted in the substrate via an exposed portion.
According to an eighteenth aspect of the invention, a semiconductor device comprises:
a plurality of conductive paths formed of a conductive material whose crystal growth is greater along the X and Y axes than along the Z axis;
a conductive film, deposited on the upper faces of the conductive paths, for which crystal growth, mainly because of plating, is greater along the Z axis;
a semiconductor chip electrically connected to the conductive paths; and
an insulating resin that is coated on the semiconductor chip and that fills separation grooves between the conductive paths, so that the conductive paths are integrally supported while the back surfaces of the conductive paths are exposed,
wherein the etched side walls of the conductive paths are curved, and at least one part of the shape of the back surface of the insulating resin substantially matches the etched side walls, and
wherein the semiconductor device is mounted in the substrate via an exposed portion.
According to a nineteenth aspect of the invention, the back surfaces of the conductive paths and the substrate are connected using brazing material, and a film for preventing the leakage of the brazing material is deposited on a connection pattern on the back surfaces of the conductive paths and/or on the substrate.
When a plurality of differently sized conductive paths is employed, the brazing material spreads so as to wet all the conductive paths, so that the thickness of the brazing material formed on the back surface of the semiconductor device varies. The same phenomenon occurs for the conductive pattern on the substrate, and due to this phenomenon, the gaps between the substrate and the conductive paths are narrowed. However, when a film resistant to the wetting to which the brazing material is susceptible is, at the least, deposited either on the substrate or on the conductive paths, a constant gap can be maintained between them.
According to a twentieth aspect of the invention, the etched face is curved substantially the same as is a face formed by non-anisotropic etching.
According to a twenty-first aspect of the invention, the back surfaces of the conductive paths are recessed more than is the back surface of the insulating resin.
According to a twenty-second aspect of the invention, an oxide is deposited on the upper surfaces of the conductive paths contacting the insulating resin.
According to a twenty-third aspect of the invention, a conductive film is deposited on the back surfaces of the conductive paths.
According to a twenty-fourth aspect of the invention, the conductive film forms an eave on the upper surfaces of the conductive paths.